Watermarks are well known marks that are imprinted on stationary, checks and the like in order to identify the manufacturer or validate products. A typical watermark is usually a semi-transparent symbol that is applied to the paper. Watermarking has expanded into digital applications to allow owners to manage who has rights to access and use certain technologies. For example, one form of electronic watermarking is to embed data into a music or video recording, and a computer or device that attempts to play it will determine whether a license to play the music or video exists based on the embedded data.
Another example of the expansion of digital watermarking is in Intellectual Property (IP) or IP core or building blocks that are used in Electronic Design Automation (EDA). IP is a block of logic or data that is used in making a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). IP blocks or cores allow repeated use of previously designed components for use in EDA. Unauthorized copying and reuse IP by infringers, however, has become an increasingly significant problem, resulting in significant losses to IP creators.
Digital watermarking has been used to combat unauthorized IP reuse by implanting a digital signature, code or identifier at a particular level of the IP design. One known watermarking system involves use of a specific set of nets, net names, cell types, etc. as input to imprint a watermark. Algorithms that are used in these netlist-based techniques modify wiring of a specific set of nets to imprint a watermark. The secret key for encoding and decoding the watermark is the knowledge of the exact set of modified nets.
Such a system may be acceptable as long as the input design data remains unchanged. However, in practice, there is rarely a case when all of the necessary information regarding particular nets is available and the netlist remains constant to allow watermark detection. Further, netlist-based techniques may not be suitable in cases when chips are submitted to a foundry and only geometrical data, such as rectangular, octangular or polygonal metal shapes is available for checking the existence of a watermak, and there are no net names and no ordering of names. Further, determining which nets exist can be difficult.
Thus, netlist-based techniques are not desirable since they rely on a netlist that should not change, and the availability of exactly this netlist (including net names or a defined ordering of nets) when the watermark must be detected. Further, small modifications to netlists can cause this particular encoding/decoding system to fail. For example, adding just one new net can break the watermark in the sense that the detector cannot locate it. Thus, changes to netlists can cause system failure, which may be one reason why these types of techniques have not been satisfactorily used within commercial layout software. Thus, netlist-based hashing or fixed net ordering are not usable in various applications.
Other known techniques involve implanting codes in the structure of layout topologies using atomic blocks and bubbles, which are points associated with a given layer. A topology describes the relative position and orientation of object pairs. A watermark is generated from the set of all topological signatures derived from a design using atomic blocks and associated primitives or bubbles. More particularly, sequences of connections between two bubbles are converted into a canonical form by removing adjacent identical edges, which form loops. The canonical form of an arbitrary topological routing is a topological signature. A watermark is formed by computing topological signatures for all of the existing topological routings and combining them.
These known techniques, however require a topological routing system to be implemented in practice. Though such systems have been studied theoretically and experimentally, they have not been successfully commercially implemented for IC layout due to various underlying difficulties. For example, modern IC layouts require the routing machinery to handle an increasingly growing set of design rules. Many rules are geometric rules that disallow certain geometric configurations or patterns. Topological routing by nature abstracts the routing from the geometrical shape based level to the topological level, in which only the relative position of objects (wires, net pins, obstructions) to each other is considered rather than the precise location of the metal shapes that realize these objects. As a result, topological routers need a subsequent geometric embedding step that may often fail as the generated topology is not realizable when precise shape locations have to be determined. Such failures can occur often and may prevent generation of legal layout and render the topological routing ineffective. Consequently, watermarking IC layouts based on such topological properties is not desirable in practice.
Thus, there exists a need for a more effective watermarking system for chip designs that does not rely on netlists and that can be implemented by existing design systems using grid or shape based routing algorithms.